The present invention concerns the coherent ordering of bus transactions in a multi-tiered bus.
Most modern computer systems include a central processing unit (CPU) and a main memory. In order to increase performance, the single CPU may be replaced, for example, by many processors with fast access to a high-bandwidth memory system. In one system, high multiprocessor performance is achieved by utilizing a tightly-coupled symmetrical multiprocessing reduced instruction set computer (RISC) processors placed on a high bandwidth coherent bus. See, for example, K. Chan, T. Alexander, C. Hu, D. Larson, N. Noordeen, Y. VanAtta, T. Wylegala, S. Ziai, Multiprocessor Features of the HP Corporate Business Servers, IEEE Compcon Digest of Papers, February 1993, pp. 336-337.
In the system described by the paper cited above, it is necessary for each processor to monitor transactions on the bus for the purpose of cache and translation look-aside buffer (TLB) coherency. When monitoring transactions, it is important for each processor to track the ordering of the transactions as well as the transactions themselves. This may be done, for example, by a transaction queue. Each processor monitors the bus. Whenever a transaction occurs on the bus, including transactions by the processor itself, the processor places the transaction in a queue. The transactions are then listed in the queue in the order in which the transactions occur on the bus.
While it is possible to use a queue to keep track of transactions for systems in which the system processors use a single processor memory bus, difficulties arise when it is necessary to track transaction order for a multi-tiered bus system. Particularly, in a multi-tiered bus system, generally some type of bus interface is used between each bus layer. Such a bus interface can add a significant amount of delay when transactions are relayed from one bus to another bus. In addition, it is desirable that each bus operates independently and simultaneously.
In such a case, all transactions on each bus can be echoed to all other busses. This will assure that each system processor will be able to observe each transaction performed on the computer system regardless of the bus to which it is connected. However, the order of transactions observed by a system processor will depend upon the particular bus to which the system processor is connected.
One way to assure that the observed transaction order is the same for all busses in the computer system is to suspend the ability of the computer system to simultaneously perform different transactions on different busses. That is, whenever a first transaction takes place on one bus, new transactions on other busses are suspended until the first transaction has propagated to the other busses. However, such suspension of bus activity can significantly impede performance of the computing system. It is desirable, therefore to implement a multi-tier bus in which each bus performs bus transactions simultaneous to the performance of bus transactions by other busses, and in which each system processor in the multi-tier bus system observes the same transaction order.